1. Field of the Invention
The present invention relates to a signal transmission system in which two signals are directed in opposite directions to each other on the same signal line.
2. Description of the Related Art
Recently, the operating speed of personal computers is increasing remarkably, and within the personal computer, data transfer is carried out between the microprocessor and memory at a cycle of from 800 MHz to 1 GHz. In this case, one cycle corresponds to about 1 ns, and data proceeds about 0.1 m on the printed board constituting the personal computer in a period of time of 1 ns. If it is assumed that the microprocessor and the memory are away from each other by 0.1 m or more, even if the microprocessor outputs data at a certain cycle, the next data is output before the previous data reaches the memory. In other words, a plurality of data exist on a transmission line connecting the microprocessor and the memory.
Moreover, normally a line for transmitting the data has bidirectionality, and in a certain cycle, the microprocessor may output write data to the memory, and in a certain cycle, the microprocessor may read out read data from the memory. As described above, since a timewise difference exists between the microprocessor and the memory, when the microprocessor tries to output data, data output from the memory may also reach the microprocessor. In such a case, a problem arises in that the microprocessor cannot recognize the data accurately. This problem will now be specifically described with reference to FIG. 6.
FIG. 6 is a block diagram showing a configuration example of a conventional signal transmission system.
The system shown in FIG. 6 includes one master device 110 and a plurality of slave devices 120 (in FIG. 6, two as an example).
The master device 110 is a device which “activates” the slave devices 120 to read/write data.
The slave devices 120 are devices which “are activated” to read/write data by the master device 110.
That is to say, at the time of read, the master device 110 transmits a read command to a certain slave device 120, and the slave device 120 returns the read data to the master device 110.
On the other hand, at the time of write, the master device 110 transmits a write command and write data to a certain slave device 120.
As is understood, in FIG. 6, all data forwarded from the master device 110 to the slave device 120 is write data, and all data forwarded from the slave device 120 to the master device 110 is read data.
In order to transmit these commands and data, each device is connected to a command bus and a data bus.
Though not shown in the figure, each signal line constituting the data bus (hereinafter referred to as a “data line”) is pulled up to 2.5 V via a resistance R1 of 50 Ω.
The master device 110 comprises a circuit for interfacing with the data bus (hereinafter referred to as “MIC”).
The MIC has the following functions:    (1) to change a potential at a connection point of the MIC and the data line, based on a value of the write data input to the MIC; and    (2) to recognize and output a value of the read data, based on the potential at the connection point of the MIC and the data line.
In FIG. 6, the MIC is input with the write data from a main circuit (not shown) in the master device 110, and outputs the read data to the main circuit.
The slave device 120 also comprises a circuit for interfacing with the data bus (hereinafter referred to as “SIC”).
The SIC has the following functions:    (1) to change a potential at a connection point of the SIC and a data line, based on a value of the read data input to the SIC; and    (2) to recognize and output a value of the write data, based on the potential at the connection point of the SIC and the data line.
In FIG. 6, the SIC is input with the read data from a main circuit (not shown) of the slave device 120, and outputs the write data to the main circuit.
In this manner, the MIC and the SIC perform mutual transformation between binary information processed by a logic circuit (for example, the main circuit) and information indicated by the potential on the data line.
Accordingly, in the description below, the binary information processed by the logic circuit is referred to as “data”, and the information indicated by the potential on the data line is referred to as a “signal”.
That is to say, on the data line, a signal indicating a value of the “read data” is referred to as a “read signal”, and a signal indicating a value of the “write data” is referred to as a “write signal”.
Moreover, in FIG. 6, the position of the master device 110 (i.e., a connection point of the master device 110 and the bus) is designated as point A, and the position of a slave device 120 adjacent to the master device 110 (i.e., a connection point of that slave device 120 and the bus) is designated as point B, and the position of a slave device 120 adjacent to that slave device 120 (i.e., a connection point of that slave device 120 and the bus) is designated as point C.
In the description below, if it is necessary to distinguish the slave device at point B from the slave device at point C, the former is referred to as “slave device B”, and the latter is referred to as “slave device C”.
Furthermore, in FIG. 6, a clock generated by a predetermined clock generator (not shown) is input, through a read clock line, in the order of slave device C, slave device B, and master device 110, and is used as a read clock in each device. The clock having reached the master device 110 is turned back by the master device 110. The turned back clock is input, through a write clock line, in the order of master device 110, slave device B, and slave device C, and is then used as a write clock in each device.
In addition, in FIG. 6, due to a propagation delay on the signal line, the time for one cycle of the clock is required for the signal to propagate between respective adjacent devices.
As described above, by assuming that the propagation delay time between respective adjacent devices is one cycle, even if a propagation delay occurs in the clock, the phase of all clocks input to each device (that is, the read clock and the write clock input to each device) becomes equal.
This hypothetical condition is for facilitating the description of a transfer timing for the command and data (see FIG. 7), by making the phase of all clocks equal, and is not for limiting the signal transmission system to which the present invention is applied. That is to say, even if the propagation delay time between respective adjacent devices is an other value (½ cycle, ⅓ cycle, etc.), the present invention is also applicable.
The operation of the signal transmission system according to the above configuration will now be described.
FIG. 7 is a timing chart showing one example of a transfer timing of commands and data. In FIG. 7, A denotes the master device 110, B denotes the slave device B, and C denotes the slave device C. Also in FIG. 7, there is shown a transfer timing when read is performed immediately after the master device 110 has performed write (that is, a read command is output immediately after the cycle in which a write command has been output).
The master device 110 first outputs a write command for writing the write data in the slave device B.
The master device 110 outputs a read command for reading the read data from the slave device C, in a cycle immediately after the cycle in which the write command has been output.
The write command and the read command reach the slave device B after a propagation delay time for one cycle, and reach the slave device C after a further propagation delay time for one cycle.
When the read command reaches the slave device C, the slave device C outputs a read signal corresponding to the read command, in a cycle immediately after the cycle in which the read command has been input.
The read signal reaches the slave device B after a propagation delay time for one cycle, and reaches the master device 110 after a further propagation delay time for one cycle.
On the other hand, the master device 110 outputs a write signal corresponding to the write command, in a cycle four cycles after the cycle in which the write command has been output.
The write signal reaches the slave device B after a propagation delay time for one cycle, and reaches the slave device C after a further propagation delay time for one cycle.
Data write to the slave device B and data read from the slave device C are performed by the above described operation.
In FIG. 7, the write signal to the slave device B and the read signal to the master device 110 reach the slave device B at the same timing. As a result, the write signal and the read signal are superimposed on each other in the slave device B, and the SIC in the slave device B cannot recognize the write data accurately.
Moreover, in FIG. 7, an example is shown in which the write signal to the slave device B is superimposed on the read signal in the slave device B. However, at the time of input of the read signal, if the master device 110 does not perform control of inhibiting the output of the write signal, the read signal for the master device 110 may be superimposed on the write signal in the master device 110. In this case, the MIC in the master device 110 cannot recognize the read data accurately.
As described above, in the conventional signal transmission system, there is a problem in that “when two signals are superimposed on each other on the same signal line, data cannot be recognized accurately.”
The above problem can be solved by shifting the output timing of the command. FIG. 8 is a timing chart showing one example of timing for solving the above problem.
In FIG. 7, the master device 110 outputs the read command in a cycle immediately after the cycle in which the write command has been output. In FIG. 8, however, the master device 110 outputs the read command in a cycle two cycles after the cycle in which the write command has been output.
Therefore, in FIG. 8, the write signal to the slave device B and the read signal to the master device 110 reach the slave device B at a different timing.
As a result, the write signal and the read signal are not superimposed on each other in the slave device B, and the SIC in the slave device B can accurately recognize the write data.
In FIG. 8, the read signal and the write signal are superimposed on each other in the slave device C, but the write signal is a signal to the slave device B, and not a signal to the slave device C. Hence the output operation of the read signal need not recognize the potential on the data line. Therefore there is no problem even if the read signal and the write signal are superimposed on each other.
In this manner, the above described problem can be solved by shifting the output timing of the command.
However, with the method shown in FIG. 8, it is necessary to delay the output timing of the command, leaving a problem in that the transmission efficiency of the bus decreases, and the command output control by the master device becomes complicated.